This invention relates to a semiconductor memory device and, more particularly, to an Electrically Erasable Programmable Read-Only-Memory device (EEPROM).
Recently there has been developed a so-called flash EEPROM which is capable of erasing memory data stored in a number of memory cells at the same time. Similarly to a dynamic memory device or a static memory device having high memory capacity, the flash EEPROM also has a memory cell array divided into a plurality of memory cell blocks. In this case, the data erase operation is performed on each of the cell blocks independently. Also in the flash EEPROM, further, there is provided a redundant memory cell block which has one or more redundant bit lines associated with redundant memory cells. As well know in the art, the redundant memory cell block is used in place of the memory cell block having a defective memory cell or cells when such a defective memory cell is accessed. Since the data erase operation is performed in cell block units, however, the redundant memory cell block, which is used in place of a certain one of the memory cell blocks, is required to be erased simultaneously erasing that memory cell block.
Referring to FIG. 5, a typical flash EEPROM includes four memory cell blocks CB1, CB2, CB3 and CB4 and a redundant memory cell block DCB. A row decoder and word driver circuit WD decodes a set of row address signals Add1 from an address buffer AB and selectively drives one of word lines WL (two word lines WL1 and WL2 being shown) which extend over the memory cell blocks CB1, CB2, CB3 and CB4 and the redundant memory cell block DCB. The memory cell blocks CB1, CB2, CB3 and CB4 and the redundant memory cell block DCB are associated with column selectors CS1, CS2, CS3, CS4 and CSD and transfer gate transistors TG1, TG2, TG3, TG4 and TGD, respectively.
Turning to FIG. 6, there is shown a circuit configuration of the memory cell block CB1 and the redundant memory cell block DCB. The other memory cell blocks CB2, CB3 and CB4 have the same configuration as the memory cell block CB1. The memory cell block CB1 has a plurality of memory cell transistors MCT111, MCT112, MCT11m, MCT121 and MCT122 arranged in rows and columns and each of them has a gate connected to one of the word lines WL, a drain connected to one of bit lines BL11, BL12, and BL1m and a source connected to a source line SL1 which is in turn connected to a common source line SL via the associated transfer gate transistor TG1. Thus, each of the memory cell block CB comprises m bit lines BL11, BL12, . . . , BL1m and one source line SL1.
On the other hand, the redundant memory cell block DCB comprises two redundant bit lines BLD1 and BLD2 and a plurality of memory cell transistors MCTD11, MCTD12. Each of the transistors has a gate connected to an associated word line, a drain connected to one of the two redundant bit lines BLD1, BLD2 and a source connected to a source line SLD.
The memory cell transistors MCT111, MCT112, MCT11m, MCT121 and MCT122 in each memory cell block CB and the memory cell transitors MCTD11, MCTD12 in the redundant memory cell block DCB are formed in the same constitution. In detail, as shown in FIG. 7, each of the memory cell transistors and the redundant memory cell transistors is of a MOS-type formed in a semiconductor substrate SUB and having a stacked type gate electrode SGE including a floating gate FGE and a control gate CGE which is connected to the word line WL1. A source region SR and a drain region DR thereof are connected to a source line SL1 and the bit line BL11, respectively.
The operation of this device will be explained on the condition that a memory cell transistor, for example the transistor MCT112, is defective. In this case, the column address designating the defective memory transistor MCT112 is programmed in an address latch circuit AL as an defective column address signal AddD1. A comparator COMP compares an input column address signal Add2 with the defective column address signal AddD1 and, if they are coincident to each other replaces, the address signal Add2 by the column address signal AddR1. Therefore, one of the redundant memory cell, the memory cell transistors MCTD11 for example, is used in place of the defective memory cell transistor MCT112.
In a program mode operation, in a case where the address signal Add which indicates the memory cell transistor MCT111 is input, the row decoder and word driver circuit WD drives the word line to a program voltage Vp, that is about 12V and supplied from a voltage controller VC1. The comparator COMP outputs the address signal Add2 as a column address signal Add3 to the column decoder CD. The program amplifier PA supplies the power voltage Vcc, that is about 5 V, via a data line DL to the column selectors CS1, CS2, CS3, CS4 and CSD. The column decoder CD decodes the address signal Add3 and outputs a column selection signal YS to the column selector CS1 which drives the bit line BL11 to the voltage Vcc. At the same time, the transfer gate transistor TG1 is turned conductive according to a control signal SC1 from a source line controller SCC responding to the address signal Add3. The voltage controller VC2 supplies the ground voltage Vgnd to a common source line SL. As a result, the channel current flows in the designated memory cell transistor, causing channel hot electrons (CHE) in the vicinity of the drain region DR thereof. These channel hot electrons are transported to the floating gate electrode FGE owing to the high voltage Vp at the control gate electrode CGE and make the threshold voltage Vt of the memory cell transistor high, for example, from about 2 V in a non-programmed state to about 7 V in a programmed state. This programmed state corresponds to a logical memory data, for example, "1". The program mode operation on any other memory cell block is performed in the same manner as above. In this device, since the each transfer gate transistor TG1, TG2, TG3, TG4 and TGD is needed to transfer the channel current of one memory cell transistor MCT111, MCT112, . . . , MCTD11 or MCTD12 only, it can be formed in a very small and common size having a same driving capability for the sake of the manufacturing processes and the integration density of the device.
In a read mode operation to read the data in the memory cell transistor MCT111, the word line WL1 is driven to the voltage Vcc and the bit line BL11 is connected to the data line DL in a same manner as above. A read amplifier RA supplies a read voltage Vr, that is about 1V, to the data line DL. The voltage controller VC2 supplies the ground voltage Vgnd to the source line SL1 via the common source line SL and the transfer transistor TG1. In this case, since the memory cell transistor MCT111 has its threshold voltage Vt about 7 V, no channel current flows therein and the voltage level at the bit line BL11 and the data line DL are maintained at the read voltage Vr. The read amplifier RA detects the voltage level at the data line DL and outputs a high level read data signal representing the logical memory data "1".
In an erase mode operation, in a case where the memory cell block CB1 is to be erased, since the redundant memory cell block DCB works as a part of the memory cell block CB1, the redundant memory cell block DCB have to be also erased. Therefore, the input address signal Add2 indicates the memory cell block CB1. The comparator COMP compares the information in the address signal Add2 indicating the memory cell block CB1 with that in the defective address signal AddD1 indicating the memory cell block CB1 so as to output the address signal Add3 which designates both of the memory cell block CB1 and the redundant memory cell block DCB. Therefore, the column selectors CS1 and CSD connect all bit lines BL11, BL12 and redundant bit lines BLD1, BLD2 therein to the data line DL which is in turn supplied with the ground voltage Vgnd from an erase controller EC. The source lines SL1 and SLD are supplied with an erase voltage Ve, that is about 12 V, from the voltage controller VC2 via the common source line SL and the transfer gate transistors TG1 and TGD. On the other hand, the row decoder and word driver circuit WD maintains all the word lines WL1 and WL2 at the ground voltage Vgnd. The semiconductor substrate SUB is maintained at the ground voltage Vgnd. Therefore, the electrons stored in the floating gate electrode FGE of the memory cell transistors MCT111, MCT112, MCT11m, MCT121 and MCT122 and the redundant memory cell transistors MCTD11 and MCTD12 which are in the programmed state are transported to the source region SR of them by the FN tunneling effect. Thus the all memory cell transistors MCT111, MCTD11, etc. in the cell blocks CB1 and DCB are regulated to be in the non-programmed state. In this case, according to the conventional memory device, it was considered that the current consumption in the erase mode operation is caused only by the FN tunneling effect in each memory cell transistor, which causes generally very little current. Therefore, while the transfer gate transistors TG1 and TGD are needed to transfer the currents caused by a plurality of memory cell transistors MCT111, MCTD11, etc. to or from the common source line SL, the transfer gate transistors TG1 and TGD has actually been formed in the common and very small size as mentioned above.
However, in this conventional device, in respect to the present invention, it is confirmed that the erase voltage Ve, which is needed to be a high level voltage such as 12 V to cause the FN tunneling, also causes a current between the source region SR and the semiconductor substrate SUB. This current is considered as a result of a tunneling effect at the PN junction between the source region SR and the substrate SUB. In particular, when the floating gate electrode FGE is filled with electrons and at a negative voltage, that is, in a programmed state, this current (referred as to PN tunneling current hereinafter) is more effectively caused and tends to be considerably larger than the FN tunneling current. Therefore, in the erase mode operation, each of the memory cell transistors MCT111, MCTD11, etc., in particular in the programmed state, causes a large current, making the total current to be transferred via each of the source lines SL1, SL2, SL3, SL4 and SLD very large. Accordingly, since the transfer gate transistors TG1, TG2, TG3, TG4 and TGD are formed in a common small size and have a very small driving capability intended for maintaining the respective source lines SL1, . . . , SL4 and SLD at the erase voltage Ve, the voltage levels at the source lines SL1, . . . , SL4 and SLD are decreased from the erase voltage Ve during the erase mode operation. Moreover, the voltage decrease at each of the source lines SL1, SL2, SL3 and SL4 is larger than that at the source line SLD owing to the large number of the memory cell transistors MCT111, MCT112, MCT11m, etc. connected thereto. Therefore, as a result, in this device, the erase mode operation on the memory cell block CB1, CB2, CB3 or CB4 needs considerably long time in comparison with the redundant memory cell block DCB. Accordingly, in a case where one of the memory cell blocks CB1, CB2, CB3 and CB4 and the redundant memory cell block DCB should be erased at the same time as explained above, if the erase mode operation is performed for a enough time to erase all memory cell transistors MCT111, MCT112, MCT11m, etc. in the memory cell block CB1, CB2, CB3 or CB4, the memory cell transistors MCTD11 and MCTD12 in the redundant memory cell block DCB is over erased, that is, the electrons in the floating gate electrode FGE thereof are transported to the source region SR more than the necessitate so that the redundant memory cell transistors MCTD11 and MCTD12 becomes depression state. Once any memory cell transistors MCTD11 and MCTD12 becomes depression state, the redundant bit lines BLD1 and BLD2 associated therewith are continuously electrically connected to the source line SLD regardless of the voltage at the word lines WL1 and WL2 so that they fails to function normally, making the total reliability of the device extremely low. On the other hand, if the erase mode operation is performed for a time only enough to erase the memory cell transistors MCTD11 and MCTD12 in the redundant memory cell block DCB, the memory cell transistors MCT111, MCT112, MCT11m, etc. in the memory cell block CB1, CB2, CB3 or CB4 are not erased sufficiently, preventing the normal function of the device.